The present invention relates generally to the manufacture of CMOS integrated circuits (ICs). More specifically, the invention relates to a method of manufacturing CMOS integrated circuits on a silicon substrate which includes a high dose deep implant in the substrate for reducing the problem of latch-up of the IC.
One of the ongoing problems associated with CMOS integrated circuits, particularly modern dynamic random access memory (DRAM) circuits, is their sensitivity to latch-up. This problem is well known in the art and is described in, for example, R. Troutman, "Latch-up in CMOS Technology: The Problem and Its Cure." Kluwer Academic, Norwell, Mass. (1986) In this reference, a high dose deep implant is used in the silicon substrate in order to reduce the latch-up problem. Generally, the higher the implant dosage, the lower the sensitivity to latch-up. However, as the dosage of the implant dopant is increased, a new problem is created. This problem is a result of the formation of defects, such as dipoles, in the substrate during the implanting process and subsequent anneal and oxidation process steps of the manufacture of the integrated circuit.
To facilitate discussion of the silicon defect problem, FIG. 1 illustrates a partial cross sectional view of a typical prior art CMOS integrated circuit silicon substrate 100 shown here at a particular point during the manufacture of the integrated circuit. Substrate 100 includes a high dose deep boron implantation region 102 (having a dose range of, for example, about 1E13-1E15 Ions/cm.sup.2) which has been formed in a previous process step. The deep boron implant process is well known in the art and therefore will not be described further herein. Although boron is used in this example as the dopant material, other dopants such as phosphorous and arsenic may be used rather than boron as is known in the art.
As shown in FIG. 1, substrate 100 has a typical CMOS IC configuration with a gate stack formed over junctions which are formed in associated P and N wells using well known IC processing techniques. Although the substrate illustrated has a particular configuration of elements formed on the substrate, the problem of the formation of dipoles in the substrate during the manufacture of the IC is a general problem associated with CMOS IC manufacturing when a high dose deep implant is used to reduce the sensitivity of the IC to latch-up regardless of the specific configuration of the elements formed on the substrate.
In the example illustrated in FIG. 1, a P-well 104 and an N-well 106 are formed into substrate 100. Also, heavily doped n-type (N+) junctions 108 and 110 are formed over P-well 104 and heavily doped p-type (P+) junctions 112 and 114 are formed over N-well 106, which are self-aligned to the gate stack. A shallow trench isolation (STI) oxide 116 is formed to separate and isolate the N+ and P+ junctions. Gate stacks 118 are formed on substrate 100. As is known in the art, gate stack 118 may be made up of a variety of different layers such as a polysilicon layer 120, a silicide layer, and/or a nitride layer 122.
As described above, a high dose deep implant is formed within substrate 100 which is used to reduce the sensitivity of the IC to latch-up. The dopant may be boron, phosphorous, arsenic, or any other conventional dopant material. As also mentioned above, generally, the higher the implant dose the lower the sensitivity to latch-up. However, once the dosage is increased above a certain critical level, the implantation process along with subsequent process steps in the manufacture of the integrated circuit causes the formation of dipoles or defects in the substrate. These dipoles or defects are illustrated in FIG. 1 by parallel lines 124, 126, and 128.
Dipoles 124, 126, and 128 are formed by the presence within the substrate of interstitials and vacancies which are not able to migrate to the surface of the silicon substrate. The substrate surface is indicated by surface 130 in FIG. 1. The interstitials are believed to be free silicon atoms which are not connected in the crystal lattice of the silicon substrate. These interstitials are released from the silicon lattice during the deep implantation process leaving behind vacancies in the silicon crystal. Generally, as long as the dose of the deep implantation is maintained below a critical dose (which is dependent on the depth of the deep implantation and the dopant used for the implantation), the interstitials and vacancies are able to migrate to surface 130 of the silicon substrate where they annihilate effectively during the various heat cycles of the manufacturing of the IC. If this is the case, the dipoles are not formed in the substrate. However, once the dosage is increased above the critical dose, all of the interstitials and vacancies are not able to either recombine or to migrate to the surface of the silicon substrate where they annihilate effectively. This leads to the formation of dipoles such as dipoles 124, 126, and 128.
As illustrated in FIG. 1, the dipoles are formed in a random manner. In some cases, a dipole such as dipole 128 may intersect a junction or other element formed on substrate 100 (as illustrated by dipole 128 intersecting junction 112 in FIG. 1). If this occurs, the dipole may cause electrical effects that can cause a failure in the IC. For example, dipole 128 may cause junction leakage from junction 112, which pulls down the potential of the junction to an incorrect level during the operation of the IC. This type of junction leakage and other electrical effects caused by dipoles may result in the unreliable operation of the IC thereby reducing the yields of IC's manufactured using high dose deep implantation substrates.
Because of the above described dipole problem, IC's manufactured using high dose deep implantation substrates typically use deep implants which limit the deep implant dosage to no greater than the critical dosage described above. In the specific example of a deep boron implant which is implanted at a depth of approximately 1-2 microns below the surface of the substrate, the critical dosage is typically about 8E.sup.13 Ions/cm.sup.2. Similarly, critical dosages for other specific deep implant substrate configurations using other dopants implanted at different depths would have critical dosages dependent on the dopant and the depth of implantation.
In order to further reduce the problem of sensitivity to latch-up, it is desirable to be able to increase the dosage above the critical dosages described above. In one approach, an additional annealing step is added to the process to reduce the probability of forming dipoles when high dose deep implant substrates are used. FIG. 2 illustrates a silicon substrate 200 similar to the substrate of FIG. 1 in that substrate 200 has the same elements as substrate 100. These elements include deep boron implant 102, P-well 104, N-well 106, N+ junctions 108 and 110, P+ junctions 112 and 114, STI oxide 116, and gate stacks 118. However, substrate 200 has been manufactured using a process which includes an additional annealing step performed after the deep boron implantation step. This annealing step involves heating the substrate for a period of time in order to allow more of the interstitials and vacancies formed during the deep implantation to migrate to the surface of the substrate where they are annihilated.
As illustrated in FIG. 2 by dipoles 202, 204, and 206, the annealing process tends to break up or reduce the formation of large dipoles. This reduces the probability that one of the dipoles, such as dipole 206 of FIG. 2, will create a strong enough electrical effect, such as junction leakage, to cause the failure of the IC. However, dipoles are still formed in the substrate and therefore may still cause defects in the IC. The annealing process simply reduces by some measure the probability of a dipole causing a failure of the IC.
In still another approach to reducing the latch-up problem, a more expensive P+ and P- substrate is used. These more expensive substrates allow the use of higher concentrations of dopant before the IC processing starts. However, in addition to the added expense of this type of substrate, this approach is limited to certain IC processes only.
Therefore, in order to further reduce the sensitivity of CMOS IC (such as DRAM circuit) to latch-up, it is desirable to be able to use higher dose deep implanting if the problem of forming dipoles within the substrate could be overcome. The present invention provides a method of producing a CMOS integrated circuit which reduces the probability that dipoles will be formed in a high dose deep implant substrate during the manufacture of the integrated circuit. This allows a higher dose deep implant to be used and therefore reduces the sensitivity to latch-up for IC's produced using this novel method.